Notifications
Clear all

nandanvanfarms.com Forum

VLSI Backend QNA

VLSI Basics

Use this forum to ask technical questions about Electronics, CMOS, semiconductors and fabrication, the basics of VLSI Design Flow etc.

 

 

Questions
0
Answers
0
Posts
0

CAD & Scripting

Use this forum to ask technical questions about Linux and Shell Scripting, TCL, PERL, Python, Automation in VLSI Design and GVIM HACKS, Flow Scripting Problems, AWK, SED, and GREP commands, etc.

 

Questions
0
Answers
0
Posts
0

Synthesis

Use this forum to ask technical questions about Synthesis Flow, Synthesis Inputs, Types of Synthesis, Optimizations in Synthesis, Timing Analysis and Debug at the Synthesis Stage, QOR analysis, Synthesis Debug, Sanity checks

 

Questions
0
Answers
0
Posts
0

Physical Design Inputs

Use this forum to ask technical questions about Synthesized Netlist, Physical Library, Design Exchanged Format (DEF), Unified Power Format (UPF), Standard Design Constraint (SDC), Technology Files, MMMC Configuration 

 

Questions
0
Answers
0
Posts
0

Floorplan

Use this forum to ask technical questions about Floorplan Overview and Steps, Pin Placement, Macro definition and placement guidelines, Physical Cells and their placement, Preplacement Power Planning PG rails

Questions
0
Answers
0
Posts
0

Placement

Use this forum to ask technical questions about Placement Overview, Pre-Placement Sanity Checks, Placement Steps, Congestion Analysis and debugging, Timing Analysis at placement stage, Placement Optimizations, Placement Quality Check, Secondary PG Routing Concepts, Timing DRC's wrt data path, Cell Density and Pin density, Global Route, Congestion Analysis.

Questions
0
Answers
0
Posts
0

Clock Tree Synthesis

Use this forum to ask technical questions about CTS Overview, CTS Spec Files, Useful Skew, CTS Steps, CTS Quality Checks, Integrated Clock Gating concepts, Signal Integrity and Crosstalk, Timing DRC's wrt. Clock Path

 

Questions
0
Answers
0
Posts
0

Routing

Use this forum to ask technical questions about Routing Overview, Route Steps, Route Quality Checks, Concept of Metal layers, VIA's definitions and types, DPT and TPT, Antenna Effect.

Questions
0
Answers
0
Posts
0

Timing (STA)

Use this forum to ask technical questions about the Basics of Timing Analysis, Combinational Timing Analysis, Sequential Timing Analysis (Setup Hold Recovery Removal), SPEF generation and related, concepts, Detailed path timing Analysis, Half Cycle and Multi-Cycle Path, Timing Analysis with PBA and GBA, OCV, AOCV, POCV Timing analysis, Prime Time, Tweaker, Tempus

 

Questions
0
Answers
0
Posts
0
Share: